Advanced gate dielectric development for VLSI technology

被引:0
|
作者
Spansion, 915 DeGuigne Dr., Sunnyvale, CA 94088, United States [1 ]
机构
来源
Mater Sci Forum | 2008年 / 133-146期
关键词
D O I
10.4028/www.scientific.net/msf.573-574.133
中图分类号
学科分类号
摘要
引用
收藏
页码:133 / 146
相关论文
共 50 条
  • [32] Line edge and gate interface roughness Simulations of advanced VLSI SOI-MOSFETs
    Herrmann, T.
    Klix, W.
    Stenzel, R.
    Duenkel, S.
    Illgen, R.
    Hoentschel, J.
    Feudel, T.
    Horstmann, M.
    SISPAD 2007: SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES 2007, 2007, : 101 - +
  • [33] Metal oxide gate electrodes for advanced CMOS technology
    Fröhlich, K
    Huseková, K
    Oszi, Z
    Hooker, JC
    Fanciulli, M
    Wiemer, C
    Dimoulas, A
    Vellianitis, G
    Roozeboom, F
    ANNALEN DER PHYSIK, 2004, 13 (1-2) : 31 - 34
  • [34] GATE ARRAYS FOR VLSI DESIGN
    FULKERSON, DE
    IEEE TRANSACTIONS ON COMPONENTS HYBRIDS AND MANUFACTURING TECHNOLOGY, 1982, 5 (01): : 133 - 137
  • [35] THIN GATE DIELECTRICS FOR VLSI
    SINGH, R
    TAYLOR, KC
    RAJKANAN, K
    CHANEY, GA
    JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1984, 131 (03) : C85 - C85
  • [36] Ultra-thin decoupled plasma nitridation (DPN) oxynitride gate dielectric for 80-nm advanced technology
    Tseng, HH
    Jeon, Y
    Abramowitz, P
    Luo, TY
    Hebert, L
    Lee, JJ
    Jiang, J
    Tobin, PJ
    Yeap, GCF
    Moosa, M
    Alvis, J
    Anderson, SGH
    Cave, N
    Chua, TC
    Hegedus, A
    Miner, G
    Jeon, J
    Sultan, A
    IEEE ELECTRON DEVICE LETTERS, 2002, 23 (12) : 704 - 706
  • [37] Challenges and opportunities in high-k gate dielectric technology
    Niwa, M
    Harada, Y
    Yamamoto, K
    Hayashi, S
    Mitsuhashi, R
    Eriguchi, K
    Kubota, M
    Hoshino, Y
    Kido, Y
    Kwong, DL
    RAPID THERMAL AND OTHER SHORT-TIME PROCESSING TECHNOLOGIES III, PROCEEDINGS, 2002, 2002 (11): : 99 - 115
  • [38] CMOS TECHNOLOGY USING PLASMA NITRIDED OXIDE AS A GATE DIELECTRIC
    STRABONI, A
    BERENGUER, M
    VUILLERMOZ, B
    DEBENEST, P
    VERNA, A
    DARS, P
    JOURNAL DE PHYSIQUE, 1988, 49 (C-4): : 421 - 424
  • [39] SrHfO3 as gate dielectric for future CMOS technology
    Rossel, C.
    Sousa, M.
    Marchiori, C.
    Fompeyrine, J.
    Webb, D.
    Caimi, D.
    Mereu, B.
    Ispas, A.
    Locquet, J. P.
    Siegwart, H.
    Germann, R.
    Tapponnier, A.
    Babich, K.
    MICROELECTRONIC ENGINEERING, 2007, 84 (9-10) : 1869 - 1873
  • [40] Layout Dependence of Gate Dielectric TDDB in HKMG FinFET Technology
    Liu, Wen
    Wu, Ernest
    Guarin, Fernando
    Griffin, Charles
    Dufresne, Roger
    Badami, Dinesh
    Shinosky, Michael
    Brochu, David
    2016 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2016,