Design and analysis of double-gate junctionless vertical TFET for gas sensing applications

被引:0
|
作者
Singh, Sonal [1 ]
Khosla, Mamta [1 ]
Wadhwa, Girish [1 ]
Raj, Balwinder [1 ]
机构
[1] Nanoelectronics Research Lab, Department of Electronics and Communication Engineering, NIT Jalandhar, Jalandhar, India
来源
关键词
D O I
暂无
中图分类号
学科分类号
摘要
25
引用
收藏
相关论文
共 50 条
  • [1] Design and analysis of double-gate junctionless vertical TFET for gas sensing applications
    Singh, Sonal
    Khosla, Mamta
    Wadhwa, Girish
    Raj, Balwinder
    APPLIED PHYSICS A-MATERIALS SCIENCE & PROCESSING, 2021, 127 (01):
  • [2] Design and analysis of double-gate junctionless vertical TFET for gas sensing applications
    Sonal Singh
    Mamta Khosla
    Girish Wadhwa
    Balwinder Raj
    Applied Physics A, 2021, 127
  • [3] Double-Gate Junctionless Transistor for Analog Applications
    Baruah, Ratul Kumar
    Paily, Roy
    JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, 2013, 13 (03) : 1802 - 1807
  • [4] Vertical Tunneling Based Dual-material Double-gate TFET
    Singh, Km Sucheta
    Kumar, Satyendra
    Nigam, Kaushal
    2021 IEEE INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION, AND INTELLIGENT SYSTEMS (ICCCIS), 2021, : 900 - 904
  • [5] Double-Gate TFET With Vertical Channel Sandwiched by Lightly Doped Si
    Kim, Jang Hyun
    Kim, Sangwan
    Park, Byung-Gook
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2019, 66 (04) : 1656 - 1661
  • [6] Double-Gate Junctionless Transistor for Low Power Digital Applications
    Baruah, Ratul Kumar
    Paily, Roy P.
    2013 1ST INTERNATIONAL CONFERENCE ON EMERGING TRENDS AND APPLICATIONS IN COMPUTER SCIENCE (ICETACS), 2013, : 23 - 26
  • [7] Design and simulation of nanoscale double-gate TFET/tunnel CNTFET
    Shashi Bala
    Mamta Khosla
    Journal of Semiconductors, 2018, (04) : 38 - 42
  • [8] Design and simulation of nanoscale double-gate TFET/tunnel CNTFET
    Bala, Shashi
    Khosla, Mamta
    JOURNAL OF SEMICONDUCTORS, 2018, 39 (04)
  • [9] Design and simulation of nanoscale double-gate TFET/tunnel CNTFET
    Shashi Bala
    Mamta Khosla
    Journal of Semiconductors, 2018, 39 (04) : 38 - 42
  • [10] Design Transmission Gates Using Double-Gate Junctionless TFETs
    Bhattacharya, Sabitabrata
    Tripathi, Suman Lata
    Nayana, G. H.
    SILICON, 2024, 16 (08) : 3359 - 3372