Design Techniques for High-Speed Wireline Transmitters

被引：7

作者：

Razavi, Behzad ^{[1
]}

机构：

[1] Department of Electrical Engineering, University of California, Los Angeles,CA,90095, United States

来源：

IEEE Open Journal of the Solid-State Circuits Society | 2021年 / 1卷

关键词：

D O I：

10.1109/OJSSCS.2021.3112398

中图分类号：

学科分类号：

摘要：

Wireline transmitters operating at tens of gigabits per second pose challenging design issues ranging from limited bandwidths to severe sensitivity to jitter. This paper presents a number of analog and digital circuit techniques that allow data rates as high as 80 Gb/s in 45-nm CMOS technology. A PAM4 prototype delivers an output swing of 630 mVppwith a clock jitter of 205 fsrmswhile drawing 44 mW. © 2021 IEEE.

引用

页码：53 / 66

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