A FPGA-based Energy-Efficient Processor for Radar-based Continuous Fall Detection

被引:0
|
作者
Chen, Juhua [1 ]
Yang, Linxin [1 ]
Ye, Wenbin [1 ]
机构
[1] Shenzhen Univ, Coll Elect & Informat Engn, Shenzhen, Peoples R China
关键词
Fall detection; convolutional neural network; FPGA; radar signal processing; low power; low cost;
D O I
10.1109/ISCAS58744.2024.10558171
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
This paper proposes a FPGA-based energy-efficient processor for radar-based continuous fall detection, consisting of a spectrogram generation circuit and a convolutional neural network (CNN). To reduce resource consumption and power usage of the entire processor, two designs were implemented: 1) A serial-FFT-based spectrogram generation circuit for radar signal preprocessing, and 2) An neural network (NN) accelerator based on row-stationary dataflow has been designed. By using the updated block wise computation technique, the accelerator enables the computation of only the NN's updated inputs, resulting in an 85% reduction in multiply-accumulate (MAC) operations and a 79% reduction in intermediate result storage. Implemented on the Xilinx FPGA board ZC702, this processor consumes only 73k LUTs, 3.6k Flip Flops (FFs), 22 Block RAMs (BRAMs), and 10 DSPs, with a power consumption of only 0302W. On an open-source radar fall detection dataset, this processor achieves an accuracy of 99.58%. The processor incurs a delay of only 0.431ms for a single preprocessing and NN inference, consuming just 130.16 mu J.
引用
收藏
页数:5
相关论文
共 50 条
  • [41] FPGA-based Annealing Processor for Ising Model
    Yoshimura, Chihiro
    Hayashi, Masato
    Okuyama, Takuya
    Yamaoka, Masanao
    2016 FOURTH INTERNATIONAL SYMPOSIUM ON COMPUTING AND NETWORKING (CANDAR), 2016, : 436 - 442
  • [42] FPGA-BASED MULTI-CORE PROCESSOR
    Wojcik, Wojciech
    Dlugopolski, Jacek
    COMPUTER SCIENCE-AGH, 2013, 14 (03): : 459 - 474
  • [43] An FPGA-based specific processor for Blokus Duo
    Olivito, Javier
    Gonzalez, Carlos
    Resano, Javier
    PROCEEDINGS OF THE 2013 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT), 2013, : 502 - 505
  • [44] SHARF: AN FPGA-BASED CUSTOMIZABLE PROCESSOR ARCHITECTURE
    Bassoy, Cem Savas
    Manteuffel, Henning
    Mayer-Lindenberg, Friedrich
    FPL: 2009 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, 2009, : 516 - 520
  • [45] An FPGA-based singular value decomposition processor
    Ma, Weiwei
    Kaye, M. E.
    Luke, D. M.
    Doraiswami, R.
    2006 CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, VOLS 1-5, 2006, : 1253 - +
  • [46] CNP: AN FPGA-BASED PROCESSOR FOR CONVOLUTIONAL NETWORKS
    Farabet, Clement
    Poulet, Cyril
    Han, Jefferson Y.
    LeCun, Yann
    FPL: 2009 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, 2009, : 32 - +
  • [47] Implementation of a kind of FPGA-based binary phase coded radar signal processor architecture
    Tian, L.-Y. (tianliyu@bit.edu.cn), 1600, Beijing Institute of Technology (21):
  • [48] Implementation of a kind of FPGA-based binary phase coded radar signal processor architecture
    田黎育
    孙密
    万阳良
    JournalofBeijingInstituteofTechnology, 2012, 21 (04) : 526 - 531
  • [49] Energy-Efficient FPGA Based Sleep Apnea Detection Using EEG Signals
    Alam, Md. Shamshad
    Siddiqui, Yasrub
    Hasan, Mohd
    Farooq, Omar
    Himeur, Yassine
    IEEE ACCESS, 2024, 12 : 40182 - 40195
  • [50] Lightweight Deep Learning Model for Radar-Based Fall Detection With Metric Learning
    Ou, Zixuan
    Ye, Wenbin
    IEEE INTERNET OF THINGS JOURNAL, 2023, 10 (09) : 8111 - 8122