Multiplexer & Memory Efficient Bit-Reversal Algorithms

This paper presents novel approaches for obtaining bit reversal. Bit reversal plays a prominent role in Fast Fourier Transform (FFT) algorithm. It is used to sort out the FFT algorithm's output, which often is in a bit-reversed order [1]. The proposed circuits consist of memories, multiplexers, counters and a bit-reversal circuit. This paper also proposes several single & dual memory-based bit-reversal circuits. The designs consume less memory and provides less latency for the calculation of bitreversal. For N (Number of inputs) = 32 & P (Number of parallel paths) = 2, the proposed approach uses 3-4 % less memory and provides 25% less latency. The proposed designs are valid for all values of N & P.