Design of a hardware-efficient floating-point multiplier with dynamic segmentation

被引：0

作者：

Tegazzini, Luca ^{[1
]}

Di Meo, Gennaro ^{[1
]}

De Caro, Davide ^{[1
]}

Strollo, Antonio G. M. ^{[1
]}

机构：

[1] Univ Napoli Federico II, DIETI, Naples, Italy

来源：

2024 19TH CONFERENCE ON PH.D RESEARCH IN MICROELECTRONICS AND ELECTRONICS, PRIME 2024 | 2024年

关键词：

Approximate computing; floating-point multiplier; low-power;

D O I：

10.1109/PRIME61930.2024.10559705

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we present a novel low-power floating-point multiplier design that leverages dynamic segmentation to enhance efficiency. Our approach approximates the mantissa product through a simple addition of dynamically extracted input segments, supplemented by an additional correction term implemented through a small, hardwired lookup table. Compared to previous proposals, our FPM shows optimal results in terms of the power-accuracy trade-off, with power savings exceeding 85% compared to an exact implementation. The proposed multiplier offers remarkable performance in image processing applications, with Structural Similarity Index (SSIM) values approaching 1 and Peak Signal-to-Noise Ratio (PSNR) reaching up to 66dB.

引用

页数：4

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