Low-Power Charge Trap Flash Memory with MoS2 Channel for High-Density In-Memory Computing

With the rise of on-device artificial intelligence (AI) technology, the demand for in-memory comptuing has surged for data-intensive tasks on edge devices. However, on-device AI requires high-density, low-power memory-based computing to efficiently handle large data volumes. Here, this study proposes a reliable multilevel, high gate-coupling ratio memory device with MoS2 channel tailored for high-density 3D NAND Flash-based in-memory computing. The MoS2 channel, featured by its small bandgap and high-mobility, facilitates reliable memory window of approximately 8 V thanks to erase operation through hole injection. This not only suppresses vertical charge loss but also alleviates the burden on voltage generator circuits, indicating the suitability of MoS2 as channel material for 3D NAND Flash architecture. Additionally, a low-k (approximate to 2.2) tunneling layer deposited via initiated chemical vapor deposition increases the gate-coupling ratio, thereby reducing the operating voltage. Utilizing Au nanoparticles as the charge storage layer, MoS2 memory devices show synaptic plasticity with 6-bit, endurance (10(4) cycles), read disturbance (10(5) cycles), and retention times (10(5) s). Furthermore, device-to-system simulations for neural networks based on MoS2-memory devices have successfully achieved a fingerprint recognition of 95.8%. These results provide the foundation to develop multi-bit MoS2-memory devices for AI accelerators and 3D NAND Flash memory.