Development of a high-performance arithmetic and logic unit for efficient digital signal processing based on reversible logic and quantum dots

被引:0
|
作者
Jun, Hu [1 ]
Wei, Xiao [1 ]
Anbar, Mohammad [2 ,3 ]
机构
[1] Yiyang Cent Hosp, Dept Cardiac Surg, Yiyang, Hunan, Peoples R China
[2] Tartous Univ, Commun Technol Engn Dept, Tartous, Syria
[3] Gulf Univ Sci & Technol, Dept Math & Nat Sci, Mishref Campus, Kuwait, Kuwait
关键词
CELLULAR-AUTOMATA; FULL-ADDER; DESIGN; QCA; IMPLEMENTATION;
D O I
10.1063/5.0189719
中图分类号
TB3 [工程材料学];
学科分类号
0805 ; 080502 ;
摘要
Digital Signal Processing (DSP) finds a wide range of applications in various fields, including telecommunications, audio and video processing, biomedical engineering, radar systems, and image processing. Previous DSP designs faced limitations in available processing power and computational resources. Insufficient processing power could result in slower execution times, an inability to handle complex algorithms, or limited capacity to process high-speed or large-scale signals. As the demand for minimal power consumption in DSP circuits continues to grow, reversible logic and quantum-dot cellular automata (QCA) have emerged as promising technologies due to their inherent ability to reduce energy loss. Within this landscape, the arithmetic and logic unit (ALU) plays a vital role in complex circuitry, serving as a key component in digital signal processing applications. However, challenges persist, including high quantum cost and the need to limit the number of cells in the ALU design. To address these challenges, our research aims to develop an efficient ALU by integrating reversible logic and QCA technology. Our focus will be on generating essential components, such as Feynman gates, Fredkin gates, and full adder circuits, which serve as foundational building blocks for reversible logic and QCA designs. These components will be combined to construct a comprehensive ALU capable of performing 20 different operations. Our implementation efforts will be centered around QCADesigner, with a specific emphasis on digital signal processing systems that prioritize energy efficiency and optimal utilization of occupied areas.
引用
收藏
页数:9
相关论文
共 50 条
  • [1] Reversible arithmetic logic unit for quantum arithmetic
    Thomsen, Michael Kirkedal
    Gluck, Robert
    Axelsen, Holger Bock
    JOURNAL OF PHYSICS A-MATHEMATICAL AND THEORETICAL, 2010, 43 (38)
  • [2] A nano-scale arithmetic and logic unit using a reversible logic and quantum-dots
    Navimipour, Nima Jafari
    Ahmadpour, Seyed-Sajad
    Yalcin, Senay
    JOURNAL OF SUPERCOMPUTING, 2024, 80 (01): : 395 - 412
  • [3] A nano-scale arithmetic and logic unit using a reversible logic and quantum-dots
    Nima Jafari Navimipour
    Seyed-Sajad Ahmadpour
    Senay Yalcin
    The Journal of Supercomputing, 2024, 80 : 395 - 412
  • [4] An Arithmetic Logic Unit Design Based on Reversible Logic Gates
    Guan, Zhijin
    Li, Wenjuan
    Ding, Weiping
    Hang, Yueqin
    Ni, Lihui
    2011 IEEE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUTERS AND SIGNAL PROCESSING (PACRIM), 2011, : 925 - 931
  • [5] REVERSIBLE/QUANTUM TERNARY ARITHMETIC LOGIC UNIT DESIGN
    Deibuk, Vitaly
    INTERNATIONAL JOURNAL OF INNOVATIVE COMPUTING INFORMATION AND CONTROL, 2016, 12 (05): : 1523 - 1533
  • [6] Optimization Approaches for Designing Quantum Reversible Arithmetic Logic Unit
    Haghparast, Majid
    Bolhassani, Ali
    INTERNATIONAL JOURNAL OF THEORETICAL PHYSICS, 2016, 55 (03) : 1423 - 1437
  • [7] Optimization Approaches for Designing Quantum Reversible Arithmetic Logic Unit
    Majid Haghparast
    Ali Bolhassani
    International Journal of Theoretical Physics, 2016, 55 : 1423 - 1437
  • [8] Classical Arithmetic Logic Unit Embedded on Reversible/Quantum Circuit
    Khan, Mozammel H. A.
    2012 15TH INTERNATIONAL CONFERENCE ON COMPUTER AND INFORMATION TECHNOLOGY (ICCIT), 2012, : 478 - 483
  • [9] Modular realization of threshold logic gates for high-performance digital signal processing applications
    Leblebici, Y
    Gurkaynak, FK
    ELEVENTH ANNUAL IEEE INTERNATIONAL ASIC CONFERENCE - PROCEEDINGS, 1998, : 281 - 285
  • [10] HIGH-PERFORMANCE DIGITAL LOGIC
    RANADA, D
    EDN MAGAZINE-ELECTRICAL DESIGN NEWS, 1979, 24 (03): : 83 - &