Design of a Low-Power Cryptographic Accelerator Under Advanced Encryption Standard

Advanced Encryption Standard (AES) has been a prevalent cryptographic structure in the world. Existing AES-related cryptographic accelerators generally face the problem of high power consumption. To deal with this challenge, this paper presents a cryptographic structure that employs iterative reuse to decrease resource utilization. Through the efficient use of delay-line RAM, the implementation of long-length key storage results in a reduction in the utilization of registers. The computational complexity of AES cryptographic algorithm is reduced by using homomorphic mapping to the inversion operation in S-box from the Galois Fields GF(2(8)) to GF[(2(4))(2)]. Such proposed AES cryptographic accelerator is characterized by its low resource utilization and low power consumption. In addition, we have also conducted some simulation analysis to evaluate its performance. The synthesis result indicates that the AES cryptographic accelerator exhibits a 0.74% reduction in utilization of LUT and a 35% decrease in power consumption, as compared to the original version. The proposed AES cryptographic accelerator results in an area of 0.101mm(2), a throughput of 12.28Gbps, and a power consumption of 2.56mW in TSMC 90nm.