Low Power CMOS Design Technique for Power Switches Gating

Power-gating is a low-power design technique to reduce leakage power. It has gained popularity in sub-100-nm CMOS designs, where leakage power is a major contributor to the overall power consumption. It utilizes power switches to power-down the logic blocks during the idle mode to reduce leakage power consumption. Power switches are used as a part of the power-gating technique to reduce the leakage power of a design. To the best of our knowledge, this is the first report in open literature to show a systematic diagnosis method for accurately diagnosing power switches. The proposed diagnosis method utilizes the recently proposed design-for-test solution for efficient testing of power switches in the presence of process, voltage, and temperature variation. It divides power switches into segments such that any faulty power switch is detectable, thereby achieving high diagnosis accuracy. This paper proposes that the analysis of Fine grain technique and Coarse grain techniques and result will be done by using the Tanner EDA tool 13.0, and calculate the power consumption.