DESIGN ASPECTS OF MOS-CONTROLLED THYRISTOR ELEMENTS - TECHNOLOGY, SIMULATION, AND EXPERIMENTAL RESULTS

We have fabricated 2.5-kV thyristor devices with integrated MOS controlled n+-emitter shorts and a bipolar turn-on gate using a p-channel DMOS technology. Square-cell geometries with pitch variations ranging from 15 to 30-mu-m were implemented in one- and two-dimensional arrays with up to 20 000 units. The impact of the cell pitch on the turn-off performance and the on-state voltage was studied for arrays with constant cathode area as well as for single-cell structures. By realizing MOS components with submicrometer channel lengths, scaled single cells are shown to turn off with current densities of several kiloamperes per square centimeter at a gate bias of 5 V. In the case of multi-cell ensembles, turn-off performance is limited due to inhomogeneous current distribution. Critical process parameters as well as the device behavior were optimized through multi-dimensional numerical simulation.