DIGIT-SERIAL PROCESSING TECHNIQUES

被引：69

作者：

HARTLEY, R ^{[1
]}

CORBETT, P ^{[1
]}

机构：

[1] PRINCETON UNIV,DEPT ELECT ENGN,PRINCETON,NJ 08544

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS | 1990年 / 37卷 / 06期

关键词：

D O I：

10.1109/31.55029

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes an architecture for hard-wired data flow algorithms which is based on the transmission of arithmetic data one digit at a time serially, and operations carried out digit-serially on that data. It is shown that digit-serial computation gives rise to particularly efficient chip designs, and that choice of digit-size allows the user to match throughput requirements to specifications. Details of the implementation of the individual operators as a cell-library of silicon CMOS circuits are given and mention is made of the software environment (silicon compiler) which allows the rapid translation of algorithms to integrated circuits. © 1990 IEEE

引用

页码：707 / 719

页数：13

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