PIPELINE ARCHITECTURES FOR RECURSIVE MORPHOLOGICAL OPERATIONS

被引:19
|
作者
SHIH, FY
KING, CT
PU, CC
机构
[1] NEW JERSEY INST TECHNOL,DEPT ELECT & COMP ENGN,NEWARK,NJ 07102
[2] NATL TSING HUA UNIV,DEPT COMP SCI,HSINCHU 300,TAIWAN
[3] NEW JERSEY INST TECHNOL,COMP VIS LAB,NEWARK,NJ 07102
[4] MING HSIN INST TECHNOL,DEPT INFORMAT MANAGEMENT,HSINCHU,TAIWAN
基金
美国国家科学基金会;
关键词
D O I
10.1109/83.350817
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
In this paper, we introduce efficient pipeline architectures for the recursive morphological operations. The standard morphological operation is applied directly on the original input image and produces an output image. The order of image scanning in which the operator is applied to the input pixels is irrelevant. However, the intent of the recursive morphological operations is to feed back the output at the current scanning pixel to overwrite its corresponding input pixel to be considered into computation at the following scanning pixels. The resultant output image by recursive morphology inherently depends on the image scanning sequence. Two pipelined implementations of the recursive morphological operations are presented. The design of an application-specific systolic array is first introduced. The systolic array uses 3 n cells to process an n x n image in 6 n - 2 cycles. The cell utilization rate is 100%. Second, a parallel program implementing the recursive morphological operations and running on distributed-memory multicomputers is described. Performance of the program can be finely tuned by choosing appropriate partition parameters.
引用
收藏
页码:11 / 18
页数:8
相关论文
共 50 条
  • [31] Programming VLIW architectures with super operations
    Aarts, BJM
    Augusteijn, A
    Aarts, EHL
    van Eijndhoven, JTJ
    MULTIMEDIA HARDWARE ARCHITECTURES 1998, 1998, 3311 : 79 - 87
  • [32] Area minimization of redundant CORDIC pipeline architectures
    Wassatsch, A
    Dolling, S
    Timmermann, D
    INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1998, : 136 - 141
  • [33] Efficient place and route for pipeline reconfigurable architectures
    Cadambi, S
    Goldstein, SC
    2000 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS, 2000, : 423 - 429
  • [34] Pipeline Reconfigurable DSP for Dynamically Reconfigurable Architectures
    Warrier, Rakesh
    Zhang, Wei
    Vun, Chan Hua
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2017, 36 (09) : 3799 - 3824
  • [35] Pipeline Reconfigurable DSP for Dynamically Reconfigurable Architectures
    Rakesh Warrier
    Wei Zhang
    Chan Hua Vun
    Circuits, Systems, and Signal Processing, 2017, 36 : 3799 - 3824
  • [36] A Dominator Path Scheduler for Deep Pipeline Architectures
    Simeonov, Aleksandar
    Medic, Slavica
    Popovic, Miroslav
    2008 6TH INTERNATIONAL SYMPOSIUM ON INTELLIGENT SYSTEMS AND INFORMATICS, 2008, : 80 - +
  • [37] Optimizing the CORDIC algorithm for processors with pipeline architectures
    1600, Publ by Elsevier Science Publishers B.V., Amsterdam, Neth
  • [38] PERFORMANCE OF PIPELINE AND PARALLEL ARCHITECTURES FOR COMMUNICATION PROCESSORS
    REDDI, AV
    COMPUTER PERFORMANCE, 1984, 5 (02): : 102 - 107
  • [39] PIPELINE ARCHITECTURES FOR DYNAMIC-PROGRAMMING ALGORITHMS
    CHEN, GH
    CHERN, MS
    JANG, JH
    PARALLEL COMPUTING, 1990, 13 (01) : 111 - 117
  • [40] Architectures for Recursive Digital Filters Using Stochastic Computing
    Liu, Yin
    Parhi, Keshab K.
    IEEE TRANSACTIONS ON SIGNAL PROCESSING, 2016, 64 (14) : 3705 - 3718