共 50 条
- [31] Programming VLIW architectures with super operations MULTIMEDIA HARDWARE ARCHITECTURES 1998, 1998, 3311 : 79 - 87
- [32] Area minimization of redundant CORDIC pipeline architectures INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1998, : 136 - 141
- [33] Efficient place and route for pipeline reconfigurable architectures 2000 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS, 2000, : 423 - 429
- [35] Pipeline Reconfigurable DSP for Dynamically Reconfigurable Architectures Circuits, Systems, and Signal Processing, 2017, 36 : 3799 - 3824
- [36] A Dominator Path Scheduler for Deep Pipeline Architectures 2008 6TH INTERNATIONAL SYMPOSIUM ON INTELLIGENT SYSTEMS AND INFORMATICS, 2008, : 80 - +
- [37] Optimizing the CORDIC algorithm for processors with pipeline architectures 1600, Publ by Elsevier Science Publishers B.V., Amsterdam, Neth
- [38] PERFORMANCE OF PIPELINE AND PARALLEL ARCHITECTURES FOR COMMUNICATION PROCESSORS COMPUTER PERFORMANCE, 1984, 5 (02): : 102 - 107