共 50 条
- [1] Area minimization of redundant CORDIC pipeline architectures INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1998, : 136 - 141
- [2] PERFORMANCE OF PIPELINE AND PARALLEL ARCHITECTURES FOR COMMUNICATION PROCESSORS COMPUTER PERFORMANCE, 1984, 5 (02): : 102 - 107
- [3] SCA - A SIMULATION-MODEL FOR CORDIC (-ALGORITHM) PROCESSORS NTZ ARCHIV, 1987, 9 (07): : 171 - 175
- [4] Reduced Memory and Low Power Architectures for CORDIC-based FFT Processors JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2012, 66 (02): : 129 - 134
- [5] Scalable Hybrid CORDIC-LUT Architectures for CG-FFT Processors 2013 9TH CONFERENCE ON PH. D. RESEARCH IN MICROELECTRONICS AND ELECTRONICS (PRIME 2013), 2013, : 105 - 108
- [6] Reduced Memory and Low Power Architectures for CORDIC-based FFT Processors Journal of Signal Processing Systems, 2012, 66 : 129 - 134
- [7] Radix-4 vectoring CORDIC algorithm and architectures INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS 1996, PROCEEDINGS, 1996, : 55 - 64
- [8] Radix-4 vectoring CORDIC algorithm and architectures JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 1998, 19 (02): : 127 - 147
- [9] Radix-4 Vectoring CORDIC Algorithm and Architectures Journal of VLSI signal processing systems for signal, image and video technology, 1998, 19 : 127 - 147