NOTE ON 3-VALUED LOGIC SIMULATION

被引:23
|
作者
BREUER, MA
机构
关键词
D O I
10.1109/TC.1972.5008985
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
引用
收藏
页码:399 / &
相关论文
共 50 条
  • [21] NEGATION AS FAILURE AND INTUITIONISTIC 3-VALUED LOGIC
    VAUZEILLES, J
    LECTURE NOTES IN ARTIFICIAL INTELLIGENCE, 1991, 535 : 227 - 241
  • [22] LEGALITY CONCEPTS FOR 3-VALUED LOGIC PROGRAMS
    NOTA, G
    OREFICE, S
    PACINI, G
    RUGGIERO, F
    TORTORA, G
    THEORETICAL COMPUTER SCIENCE, 1993, 120 (01) : 45 - 68
  • [23] ON SHEFFER SYMMETRIC FUNCTIONS IN 3-VALUED LOGIC
    STOJMENOVIC, I
    DISCRETE APPLIED MATHEMATICS, 1989, 22 (03) : 267 - 274
  • [24] GENTZENS TECHNIQUES IN 3-VALUED LOGIC OF LUKASIEWICZ
    BECCHIO, D
    PABION, JF
    JOURNAL OF SYMBOLIC LOGIC, 1977, 42 (01) : 123 - 124
  • [25] 3-VALUED BROUWER-ZADEH LOGIC
    GIUNTINI, R
    INTERNATIONAL JOURNAL OF THEORETICAL PHYSICS, 1993, 32 (10) : 1875 - 1887
  • [26] 3-WIRE 3-VALUED LOGIC CIRCUITS
    HARADA, N
    SHIMADA, R
    TAMESADA, T
    ELECTRONICS & COMMUNICATIONS IN JAPAN, 1969, 52 (01): : 120 - &
  • [27] Fixpoint 3-valued semantics for autoepistemic logic
    Denecker, M
    Marek, V
    Truszczynski, M
    FIFTEENTH NATIONAL CONFERENCE ON ARTIFICIAL INTELLIGENCE (AAAI-98) AND TENTH CONFERENCE ON INNOVATIVE APPLICATIONS OF ARTIFICAL INTELLIGENCE (IAAI-98) - PROCEEDINGS, 1998, : 840 - 845
  • [28] 3-VALUED SIMULATION OF DIGITAL SYSTEMS
    MOR, M
    IEEE TRANSACTIONS ON COMPUTERS, 1976, 25 (11) : 1152 - 1156
  • [29] Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values
    Kajihara, S
    Saluja, KK
    Reddy, SM
    ETS 2004: NINTH IEEE EUROPEAN TEST SYMPOSIUM, PROCEEDINGS, 2004, : 108 - 113
  • [30] Static program analysis via 3-valued logic
    Reps, TW
    Sagiv, M
    Wilheim, R
    COMPUTER AIDED VERIFICATION, 2004, 3114 : 15 - 30