A FAULT-TOLERANT ASSOCIATIVE MEMORY WITH HIGH-SPEED OPERATION

被引：9

作者：

BERGH, H ^{[1
]}

ENELAND, J ^{[1
]}

LUNDSTROM, LE ^{[1
]}

机构：

[1] ELLEMTEL UTVECKLINGS AB,S-12525 ALVSJO,SWEDEN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1990年 / 25卷 / 04期

关键词：

D O I：

10.1109/4.58283

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An 8-kb (128 word × 64 b) CMOS associative memory with word- and bit-parallel operation is described. The highly parallel and pipelined architecture was optimized for high-speed associative operations. The data processing capability is one word/cycle corresponding to 16 MIPS at a typical cycle time of 60 ns. The memory is fault tolerant under software control. A faulty word location in the memory can be made inaccessible by on-chip circuitry. The device is a complete singlechip associative memory with internally controlled addressing and associative data as output. © 1990 IEEE

引用

页码：912 / 919

页数：8

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