AN ASIP INSTRUCTION SET OPTIMIZATION ALGORITHM WITH FUNCTIONAL MODULE SHARING CONSTRAINT

One of the most interesting and most analyzed aspects of the CPU design is the instruction set design. How many and which operations to be provided by hardware is one of the most fundamental issues relating to the instruction set design. This paper describes a novel method that formulates the instruction set design of ASIP (an Application Specific Integrated Processor) using a combinatorial approach. Starting with the whole set of all possible candidate instructions that represent a given application domain, this approach selects a subset that maximizes the performance under the constraints of chip area, power consumption, and functional module sharing relation among operations. This leads to the efficient implementation of the selected instructions. A branch-and-bound algorithm is used to solve this combinatorial optimization problem. This approach selects the most important instructions for a given application as well as optimizing the hardware resources that implement the selected instructions. This approach also enables designers to predict the performance of their design before implementing them, which is a quite important feature for producing a quality design in reasonable time.