MULTIPLIERLESS ARRAY ARCHITECTURE FOR COMPUTING DISCRETE COSINE TRANSFORM

被引：4
|
作者：
MANDAL, MC [1 ]
DHAR, AS [1 ]
BANERJEE, S [1 ]
机构：
[1] INDIAN INST TECHNOL,DEPT ELECTR & ELECT COMMUN ENGN,KHARAGPUR 721302,W BENGAL,INDIA
来源：
COMPUTERS & ELECTRICAL ENGINEERING | 1995年 / 21卷 / 01期
关键词：
GIVENS ROTOR; ARRAY ARCHITECTURE; DCT;
D O I：
10.1016/0045-7906(94)00013-7
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
An array architecture for parallel computation of Discrete Cosine Transform (DCT) is presented. Multiplierless Givens rotors are employed as processing elements ensuring an economic usage of floor space. The interconnection pattern between the constituent linear arrays is determined by a permutation cycle involving a primitive root of the transform length that also governs the spatial sequence of the transform output points.
引用
收藏
页码：13 / 19
页数：7
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