MULTIPLIERLESS ARRAY ARCHITECTURE FOR COMPUTING DISCRETE COSINE TRANSFORM

被引：4
|
作者：
MANDAL, MC [1 ]
DHAR, AS [1 ]
BANERJEE, S [1 ]
机构：
[1] INDIAN INST TECHNOL,DEPT ELECTR & ELECT COMMUN ENGN,KHARAGPUR 721302,W BENGAL,INDIA
来源：
COMPUTERS & ELECTRICAL ENGINEERING | 1995年 / 21卷 / 01期
关键词：
GIVENS ROTOR; ARRAY ARCHITECTURE; DCT;
D O I：
10.1016/0045-7906(94)00013-7
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
An array architecture for parallel computation of Discrete Cosine Transform (DCT) is presented. Multiplierless Givens rotors are employed as processing elements ensuring an economic usage of floor space. The interconnection pattern between the constituent linear arrays is determined by a permutation cycle involving a primitive root of the transform length that also governs the spatial sequence of the transform output points.
引用
收藏
页码：13 / 19
页数：7
相关论文
共 50 条
  • [1] UNIFIED ARRAY ARCHITECTURE FOR DISCRETE COSINE TRANSFORM, SINE TRANSFORM AND THEIR INVERSES
    GUO, JI
    CHEN, CS
    JEN, CW
    ELECTRONICS LETTERS, 1995, 31 (21) : 1811 - 1812
  • [2] A new multidimensional recursive architecture for computing the discrete cosine transform
    Elnaggar, A
    Alnuweiri, HM
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 2000, 10 (01) : 113 - 119
  • [3] COMPUTING DISCRETE COSINE TRANSFORM
    TSENG, BD
    MILLER, WC
    IEEE TRANSACTIONS ON COMPUTERS, 1978, 27 (10) : 966 - 968
  • [4] A NEW ARRAY ARCHITECTURE FOR PRIME-LENGTH DISCRETE COSINE TRANSFORM
    GUO, JI
    LIU, CM
    JEN, CW
    IEEE TRANSACTIONS ON SIGNAL PROCESSING, 1993, 41 (01) : 436 - 442
  • [5] Fast algorithm for computing discrete cosine transform
    Kok, CW
    IEEE TRANSACTIONS ON SIGNAL PROCESSING, 1997, 45 (03) : 757 - 760
  • [6] FAST ALGORITHMS FOR COMPUTING THE DISCRETE COSINE TRANSFORM
    CHAN, SC
    HO, KL
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1992, 39 (03): : 185 - 190
  • [7] A novel linear array for discrete cosine transform
    Shieh, Yaw-Shih
    Sung, Tze-Yun
    Hsin, Hsi-Chin
    WSEAS Transactions on Circuits and Systems, 2010, 9 (05): : 335 - 346
  • [8] An improved architecture for the adaptive discrete cosine transform
    Martin, F
    Bull, DR
    ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 2, 1996, : 742 - 745
  • [9] SYSTOLIC ARCHITECTURE FOR INVERSE DISCRETE COSINE TRANSFORM
    CHANG, YT
    WANG, CL
    ELECTRONICS LETTERS, 1995, 31 (21) : 1809 - 1811
  • [10] Systolic architecture for inverse discrete cosine transform
    Natl Tsing Hua Univ, Hsinchua, Taiwan
    Electron Lett, 21 (1809-1811):
12345