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- [31] EFFICIENT BIT-LEVEL SYSTOLIC ARRAY FOR THE LINEAR DISCRIMINANT FUNCTION CLASSIFIER IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS, 1987, 134 (05): : 216 - 224
- [32] A HIGH-PERFORMANCE BIT-LEVEL SYSTOLIC ARRAY FOR IIR FILTERING CA-DSP 89, VOLS 1 AND 2: 1989 INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SIGNAL PROCESSING, 1989, : 553 - 557
- [33] SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation 11TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN - ARCHITECTURES, METHODS AND TOOLS : DSD 2008, PROCEEDINGS, 2008, : 566 - 571
- [38] Bit-level systolic array for FIR filter using AND-based Bit-serial multiplier IEEE TENCON 2003: CONFERENCE ON CONVERGENT TECHNOLOGIES FOR THE ASIA-PACIFIC REGION, VOLS 1-4, 2003, : 87 - 90
- [39] Bit-GraphBLAS: Bit-Level Optimizations of Matrix-Centric Graph Processing on GPU 2022 IEEE 36TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM (IPDPS 2022), 2022, : 515 - 525
- [40] A VLSI design of high speed bit-level Viterbi decoder 2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 2006, : 309 - +