A BIPOLAR DIVIDED WORD-LINE SCHEME FOR A HIGH-SPEED AND LARGE-CAPACITY BICMOS SRAM

A divided word-line scheme which uses a bipolar current-switch circuit is proposed. This structure allows high-speed and low-power operation by reducing the logic swing in the long main word lines and decreasing the current in the nonselected decoder. Two key circuits, the bipolar main decoder and the section decoder, are described in detail. These circuits, with a bipolar two-level cascode current-switch circuit, enable the SRAM to operate on a low external supply voltage. To demonstrate the effectiveness of this concept, an ECL100K interface 256-kb SRAM is designed and fabricated using 0.8-mum BiCMOS technology. A typical address access time of 5.5 ns and the power consumption of 750 mW are obtained.