APPLICATION-SPECIFIC CMOS OUTPUT DRIVER CIRCUIT-DESIGN TECHNIQUES TO REDUCE SIMULTANEOUS SWITCHING NOISE

被引:58
|
作者
SENTHINATHAN, R [1 ]
PRINCE, JL [1 ]
机构
[1] UNIV ARIZONA,DEPT ELECT & COMP ENGN,CTR ELECTR PACKAGING RES,TUCSON,AZ 85721
关键词
11;
D O I
10.1109/4.262016
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Application specific CMOS circuit design techniques to reduce simultaneous switching noise (SSN-also known as Delta-I noise or ground bounce) were analyzed. Detailed investigation on the CMOS output driver switching current components was performed. The limitations in using current controlled (CC) CMOS output drivers in high-speed (> 30 MHz) design applications are explained. Application specific, high-speed, controlled slew rate (CSR) CMOS output drivers were studied and designed. For a given device channel length, once the predriver and driver device sizes are fixed, the performance (speed, switching noise, sink/source capabilities) is determined. With controlled slew rate output drivers, more than 50% improvement was found in the input receiver noise immunity (measure of maximum tolerable SSN) compared to conventional drivers, while the speed and sink/source capabilities are preserved. This effective SSN reduction improvement is achieved with only a small increase in output driver silicon area. The CSR output driver uses distributed and weighted switching driver segments to control the output driver's slew rate for a given load capacitance. These CSR CMOS output drivers were compared with standard CMOS output drivers, showing significant reduction in effective switching noise pulse width.
引用
收藏
页码:1383 / 1388
页数:6
相关论文
共 37 条
  • [1] Simultaneous switching noise of CMOS output buffers
    Gutzmann, M
    ELECTROMAGNETIC COMPATIBILITY 1996 - THIRTEENTH INTERNATIONAL WROCLAW SYMPOSIUM, 1996, : 253 - 257
  • [2] EFFECT OF CMOS DRIVER LOADING CONDITIONS ON SIMULTANEOUS SWITCHING NOISE
    VAIDYANATH, A
    THORODDSEN, B
    PRINCE, JL
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART B-ADVANCED PACKAGING, 1994, 17 (04): : 480 - 485
  • [3] Analysis of simultaneous switching noise by short-circuit current in CMOS-single ended driver
    Kim, YJ
    Han, SW
    Park, KW
    Wee, JK
    Kih, JS
    55th Electronic Components & Technology Conference, Vols 1 and 2, 2005 Proceedings, 2005, : 1748 - 1751
  • [4] Application-specific Arithmetic Circuit Design for a Particle Tracking Application
    Kambe, Takashi
    Takehara, Kohsei
    Tsukiyama, Shuji
    2013 IEEE 4TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS (LASCAS), 2013,
  • [5] Design and Verification of the Programming Circuit in an Application-Specific FPGA
    Yang, Zhichao
    Chen, Stanley L.
    Liu, Zhongli
    2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 2039 - 2042
  • [6] Device-Modeling and Circuit-Design Techniques for CMOS Transceivers in THz Region
    Fujimoto, Ryuichi
    Fujishima, Minoru
    2011 IEEE 54TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2011,
  • [7] Design of a new CMOS output buffer with low switching noise
    Yang, L
    Yuan, JS
    ICM 2003: PROCEEDINGS OF THE 15TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, 2003, : 131 - 134
  • [8] CELL LIBRARIES AND ASSEMBLY TOOLS FOR ANALOG DIGITAL CMOS AND BICMOS APPLICATION-SPECIFIC INTEGRATED-CIRCUIT DESIGN
    SMITH, MJS
    PORTMANN, C
    ANAGNOSTOPOULOS, C
    TSCHANG, PS
    RAO, R
    VALDENAIRE, P
    CHING, H
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (05) : 1419 - 1432
  • [9] LOGIC-SYSTEM DESIGN TECHNIQUES REDUCE SWITCHING-CMOS POWER
    WAKEMAN, L
    EDN MAGAZINE-ELECTRICAL DESIGN NEWS, 1984, 29 (09): : 243 - &
  • [10] Simultaneous switching noise analysis using application specific device modeling
    Ding, L
    Mazumder, P
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2003, 11 (06) : 1146 - 1152