FAST MULTIPLIER DESIGN USING REDUNDANT SIGNED-DIGIT NUMBERS

A high speed multiplier design is presented using redundant binary signed-digit number representation internally while the input operands and the output product are in two's complement form. The design of a carry free redundant binary signed-digit (RBSD) adder cell is presented. The multiplication algorithm uses bit-pair recording to generate the partial products. The partial products are added in the form of a binary tree using carry free RBSD adder cells. The regular structure of these adder cells results in a multiplier design that is suitable for VLSI implementation. The increased speed is achieved through the carry free addition of partial products using redundant signed-digit numbers. The use of a recoding scheme will reduce the number of rows of partial products by a factor of two. The proposed multiplier design has a multiplication time of order O(log2 n) and area-time complexity of order O(n2 log2 n) for a word length of n. © 1990 Taylor & Francis Ltd.