In order to fabricate 1 Gbit dynamic random access memories, or DRAMs, with 0.15 mum minimum features using X-ray lithography, the total overlay error must be no more than 0.05 mum. We assign 0.03 mum to the budget for mask distortion overlay error, which can be subdivided into fabrication-process-induced distortion (0.024 mum), fixturing-induced distortion (0.01 mum), and X-ray exposure-induced distortion (0.01 mum). We study, through theoretical models, these sources of distortion. In our mask-making process, a 75-mm-dia., 0.6-mm-thick Si wafer coated with 1-mum-thick SiC is direct-bonded to a 100-mm-dia., 4-mm-thick Si frame. Tungsten absorber is patterned on the SiC film, and then the wafer is back-etched to form the membrane window. The mask frame opening is used as the back-etching mask. We found that in order to meet the budget for the fabrication-process-induced distortion for a 46-mm-dia. SiC membrane (corresponding to the area of two 1 Gbit DRAM chips) and a target membrane stress of 1 x 10(9) dyn/cm2, the nonuniformity in the membrane stress or thickness must be under 2% and the absorber stress no more than 5 X 10(7) dyn/cm2. High X-ray exposure power leads to a temperature rise of the mask. We found that as long as the X-ray exposures are performed in helium, the distortion in the printed image is within budget, even at high exposure intensities (340 mW/cm2 absorbed power). We also determine that a properly designed three-point mask-holding fixture is sufficient to meet the budget for fixturing induced distortion.
