A 12-bit 40-MS/s SHA-less pipelined ADC using a front-end RC matching technique

A 12-Bit 40-MS/s pipelined analog-to-digital converter ( ADC) incorporates a front-end RC constant matching technique and a set of front-end timing with different duty cycle that are beneficial for enhancing linearity in SHA-less architecture without tedious verification in back-end layout simulation. Employing SHA-less, opampsharing and low-power opamps for low dissipation and low cost, designed in 0.13-mu m CMOS technology, the prototype digitizes a 10.2-MHz input with 78.2-dB of spurious free dynamic range, 60.5-dB of signal-to-noiseand- distortion ratio, and -75.5-dB of total harmonic distortion (the first 5 harmonics included) while consuming 15.6-mW from a 1.2-V supply.