A Scalable Configurable Architecture for Advanced Wireless Communication Algorithms

We propose a configurable and scalable architecture targeted for the implementation of advanced wireless communication algorithms based on matrix computations. A design methodology for programming and configuring the processor architecture is developed. The design entry point is the representation of the algorithm in Matlab/Simulink. The Simulink description is parsed and the algorithm’s Dependence Flow Graph is derived, which is scheduled and space–time mapped onto the proposed architecture. The compiler reconfigures the switch boxes of the proposed hierarchical interconnection network in the architecture. An energy consumption model is derived, and design examples are provided that demonstrate the enhanced energy efficiency of the proposed architecture compared to a state of the art programmable VLIW DSP processors.