Comparative Analysis of Noise Behavior of Highly Doped Double Pocket Double-Gate and Single-Gate Negative Capacitance FET

被引:0
|
作者
Jagritee Malvika
Vivek Talukdar
Bijit Kumar
Kavicharan Choudhuri
机构
[1] National Institute of Technology Silchar,Department of Electronics and Communication Engineering
[2] Indian Institute of Technology Bombay,Department of Electrical Engineering
来源
关键词
Negative capacitance; HDDP-DG-NCFET; SG-NCFET; power spectral density; noise degradation; temperature;
D O I
暂无
中图分类号
学科分类号
摘要
This work employs comparative analysis to explore the noise behavior of a single-gate negative capacitance field-effect transistor (SG-NCFET) and highly doped double pocket double-gate negative capacitance FET (HDDP-DG-NCFET). This study examines the voltage noise power spectral density (Svg) and current noise power spectral density (Sid) under the effects of scaling and varying factors such as ferroelectric thickness (Tfe), dielectric material, oxide thickness (Tox), frequency and varying temperatures (200–400 K). The results show that the values of Sid and Svg are better for the HDDP-DG-NCFET than the SG-NCFET device. The study also reveals that generation recombination (G–R) noise of net power spectral densities predominates primarily at lower and medium frequencies, whereas diffusion noise predominates at higher frequencies. Similarly, it is observed that the flicker noise is notable at lower frequencies. In addition, this investigation emphasize on the examination of net Svg with regard to frequency for various ferroelectric thicknesses, which shows that the lowest Svg is achieved at 10 Hz for Tfe = 7 nm as compared to various ferroelectric thicknesses. Finally, the temperature study of the noise performance revealed that, the impact of increased noise is more pronounced at small gate voltages (Vg) and lower temperatures, with G–R noise as the predominating noise component.
引用
收藏
页码:6203 / 6215
页数:12
相关论文
共 50 条
  • [41] Analytical Model for Junctionless Double-Gate FET in Subthreshold Region
    Shin, Yong Hyeon
    Weon, Sungwoo
    Hong, Daesik
    Yun, Ilgu
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2017, 64 (04) : 1433 - 1440
  • [42] Performance of Double Gate Tunnel FET Devices with Source Pocket
    Mishra, Varun
    Verma, Yogesh Kumar
    Verma, Prateek Kishor
    Singh, Ningthoujam Qoonand
    Gupta, Santosh Kumar
    ADVANCES IN VLSI, COMMUNICATION, AND SIGNAL PROCESSING, 2020, 587 : 387 - 395
  • [43] Negative capacitance double-gate MOSFET for advanced low-power electronic applications
    Kumar, Amit
    Communication, Saurabh Chaturvedi
    Kumar, Satyendra
    MICROELECTRONICS JOURNAL, 2025, 159
  • [44] Impact of Interface Traps on Reliability in Negative Capacitance Source Pocket Double Gate TFET
    Babu, K. Murali Chandra
    Goel, Ekta
    ARABIAN JOURNAL FOR SCIENCE AND ENGINEERING, 2025,
  • [45] On gate stack scalability of double-gate negative-capacitance FET with ferroelectric HfO2 for energy efficient sub-0.2V operation
    Jang, Kyungmin
    Saraya, Takuya
    Kobayashi, Masaharu
    Hiramoto, Toshiro
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2018, 57 (02)
  • [46] Scalability study on a capacitorless 1T-DRAM: From single-gate PD-SOI to double-gate FinDRAM
    Tanaka, T
    Yoshida, E
    Miyashita, T
    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, : 919 - 922
  • [47] Impact of different ground planes of UTBB SOI MOSFETs under the single-gate (SG) and double-gate (DG) operation mode
    Othman, Noraini
    Arshad, M. K. Md
    Hashim, S. N. Sabki U.
    2014 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS (ICSE), 2014, : 88 - 91
  • [48] Design of Enhancement Mode Single-gate and Double-gate Multi-channel GaN HEMT with Vertical Polarity Inversion Heterostructure
    Feng, Peijie
    Teo, Koon Hoo
    Oishi, Toshiyuki
    Yamanaka, Koji
    Ma, Rui
    2013 25TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD), 2013, : 203 - 206
  • [49] Capacitance modeling of short-channel double-gate MOSFETs
    Borli, Hakon
    Kolberg, Sigbjorn
    Fjeldly, Tor A.
    SOLID-STATE ELECTRONICS, 2008, 52 (10) : 1486 - 1490
  • [50] Simulation of OTA's with Double-Gate Graded-Channel MOSFETS using the Symmetric Doped Double-Gate Model
    Contreras, E.
    Cerdeira, A.
    Pavanello, M. A.
    MICROELECTRONICS TECHNOLOGY AND DEVICES - SBMICRO 2010, 2010, 31 (01): : 75 - 81