On design and performance analysis of improved shuffle exchange gamma interconnection network layouts

Multistage Interconnection Networks (MINs) are an effective means of communication between multiple processors and memory modules in many parallel processing systems. Literature consists of numerous fault-tolerant MIN designs. However, due to the recent advances in the field of parallel processing, requiring large processing power, an increase in the demand to design and develop more reliable, cost-effective and fault-tolerant MINs is being observed. This work proposes two novel MIN designs, namely, Augmented-Shuffle Exchange Gamma Interconnection Network (A-SEGIN) and Enhanced A-SEGIN (EA-SEGIN). The proposed MINs utilize chaining of switches, and multiplexers & demultiplexers for providing a large number of alternative paths and thereby better fault tolerance. Different reliability measures, namely, 2-terminal, multi-source multi-destination, broadcast and network/global, respectively, of the proposed MINs have been evaluated with the help of all enumerated paths and well-known Sum-of-Disjoint Products approach. Further, overall performance, with respect to the number of paths, different reliability measures, hardware cost and cost per unit, of the proposed MINs has been compared with 19 other well-studied MIN layouts. The results suggest that the proposed MINs are very strong competitors of the preexisting MINs of their class owing to their better reliability and cost effectiveness.