Vertical Dopingless Dual-Gate Junctionless FET for Digital and RF Analog Applications

This paper presents the design and analysis of a vertical dopingless double gate junctionless field-effect transistor (VDL-DG-JLFET) on a silicon-on-insulator (SOI) substrate, utilizing the charge plasma concept. 2D TCAD numerical simulations have been carried out to evaluate and compare switching and analog/ RF performance parameters with a vertical double gate junctionless accumulation field-effect transistor (VDG-JAMFET). The results demonstrate that the VDL-DG-JLFET exhibits superior gate control and delivers substantial enhancements in critical parameters such as drive current (ID), reduction of drain-induced barriers (DIBL), subthreshold swing (SS), and the on-current to off-current ratio (ION/IOFF) when juxtaposed with the VDG-JAMFET. Additionally, the VDL-DG-JLFET demonstrates improved transconductance (gm), cut-off frequency (fT), and maximum oscillation frequency (fmax) compared to the VDG-JAMFET. These findings collectively highlight the superior attributes of the VDL-DG-JLFET in comparison to the VDG-JAMFET, reinforcing its potential for advanced electronic applications.