A scheme of GA acceleration based on domain generic IC

GA Acceleration based on GPU + CPU is no vantage in its area and power consumption. In this paper, we established an innovative chip structure of domain general integrated circuit (DGIC) to sever as a scheme of the IoT node, in which mainly involves the virtualization technology of cloud computing, including the resource virtualization and the virtualization architecture. Take these virtualized IP core component resources as concrete execution step to form a semantic process, and its execution can be driven by an engine of the virtualization architecture. Through restructure of its semantic process, an application scenario can be expressed as a names series of these logical resources, so such it is mapped to its virtualized resources set step-by-step. In this way, as an ASIC, a DGIC chip is endowed with the CPU’s characteristics that can update its program flow to adapt to diverse application scenarios. In this paper, we delivered a DGIC sample in the GA acceleration domain, and tested a genetic algorithm based on Xilinx FPGA V5. Its acceleration ratio is notably better than the present GPU + CPU approach, while its valuable advantages are in its size and power consumption.