A buffer overflow detection and defense method based on RISC-V instruction set extension

被引:0
|
作者
Chang Liu
Yan-Jun Wu
Jing-Zheng Wu
Chen Zhao
机构
[1] Chinese Academy of Sciences,Intelligent Software Research Center, Institute of Software
[2] University of Chinese Academy of Sciences,State Key Laboratory of Computer Science, Institute of Software
[3] Chinese Academy of Sciences,undefined
来源
关键词
RISC-V; Operating system security; Buffer overflow; Control flow hijacking; NX bit; Xibop;
D O I
暂无
中图分类号
学科分类号
摘要
引用
收藏
相关论文
共 50 条
  • [21] An FFT Accelerator Using Deeply-coupled RISC-V Instruction Set Extension for Arbitrary Number of Points
    Jiang, Shijie
    Zou, Yi
    Wang, Hao
    Li, Wanwan
    2023 IEEE 34TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, ASAP, 2023, : 165 - 171
  • [22] A Reconfigurable Convolutional Neural Network-Accelerated Coprocessor Based on RISC-V Instruction Set
    Wu, Ning
    Jiang, Tao
    Zhang, Lei
    Zhou, Fang
    Ge, Fen
    ELECTRONICS, 2020, 9 (06) : 1 - 19
  • [23] RV-CNN: Flexible and Efficient Instruction Set for CNNs Based on RISC-V Processors
    Lou, Wenqi
    Wang, Chao
    Gong, Lei
    Zhou, Xuehai
    ADVANCED PARALLEL PROCESSING TECHNOLOGIES (APPT 2019), 2019, 11719 : 3 - 14
  • [24] Implementation and Extension of Bit Manipulation Instruction on RISC-V Architecture using FPGA
    Jain, Vineet
    Sharma, Abhishek
    Bezerra, Eduardo Augusto
    2020 IEEE 9TH INTERNATIONAL CONFERENCE ON COMMUNICATION SYSTEMS AND NETWORK TECHNOLOGIES (CSNT 2020), 2020, : 167 - 172
  • [25] Simulation and Formal: The Best of Both Domains for Instruction Set Verification of RISC-V Based Processors
    Duran, Ckristian
    Morales, Hanssel
    Rojas, Camilo
    Ruospo, Annachiara
    Sanchez, Ernesto
    Roa, Elkim
    2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2020,
  • [26] Design of a Convolutional Neural Network Instruction Set Based on RISC-V and Its Microarchitecture Implementation
    Jiao, Qiang
    Hu, Wei
    Wen, Yuan
    Dong, Yong
    Li, Zhenhao
    Gan, Yu
    ALGORITHMS AND ARCHITECTURES FOR PARALLEL PROCESSING, ICA3PP 2020, PT II, 2020, 12453 : 82 - 96
  • [27] MiniRV: A Subcompact RISC-V Core with Optimized Instruction Set for Chiplet System
    Xiong, Jie
    Cui, Yang
    Yang, Zhuo
    Gao, Hao
    Zheng, Pan
    Cai, Wenwen
    Zhang, Li
    IEICE ELECTRONICS EXPRESS, 2025,
  • [28] A RISC-V Instruction Set Processor-Micro-architecture Design and Analysis
    Raveendran, Aneesh
    Patil, Vinayak Baramu
    Selvakumar, David
    Desalphine, Vivian
    2016 INTERNATIONAL CONFERENCE ON VLSI SYSTEMS, ARCHITECTURES, TECHNOLOGY AND APPLICATIONS (VLSI-SATA), 2016,
  • [29] RISC-V Extension for Lightweight Cryptography
    Tehrani, Etienne
    Graba, Tarik
    Merabet, Abdelmalek Si
    Danger, Jean-Luc
    2020 23RD EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2020), 2020, : 222 - 228
  • [30] A Fault Attack Resistant Method for RISC-V Based on Interrupt Handlers and Instruction Extensions
    Wei, Jiashuo
    Liu, Qiang
    2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024, 2024,