Performance evaluation of hetero-stacked TFET for variation in lateral straggle and its application as digital inverter

This paper reports the effect of variation in lateral straggle parameter on electrical parameters in hetero-stacked TFET (HS-TFET) through technology computer aided design simulator. Extension of the source/drain dopant into the channel region affects the performance of the device significantly. To optimize the performance of the HS-TFET, various parameters such as drain current (ID), subthreshold swing (SS), transconductance (gm), output conductance (gd), capacitances (Cgg, Cgs, and Cgd) and the cut-off frequency (fT) for variation in lateral straggle parameter from 0 to 8 nm is investigated. Higher value of lateral straggle results in increased in the lateral electric field which increases the ON current of the device, but the subthreshold swing deteriorates due to decrease in the effective channel length. The circuit performance of the HS-TFET is investigated using a digital inverter for variation in lateral straggle parameter.