Dual-time resolution time-based transceiver for low-power serial interfaces

A dual-time resolution differential-time signaling (DTR-DTS) architecture is proposed in this paper. The number of transmitted bits per symbol in a time-based serial link can be increased by using dual-time resolution pulse-position modulation at the transmitter side instead of using the conventional pulse-position modulation without significantly affecting the transmitted signal bandwidth. Using the proposed architecture, the receiver design is simplified by using time-to-digital converter (TDC) circuits with less number of bits compared to the differential-time signaling (DTS) architecture for the same link rate. The design details are presented in this paper. A simulated 8-bit 12 Gb/s DR-DTS link has been designed in 65 nm mixed signal CMOS process using Cadence tools. Four TDC circuits, 2-bits each, have been used to recover the 8-bits from the received signal. The simulated DTR-DTS link consumes 3.6 mW without the driver circuit.