Throughput analysis for input-buffered ATM switches with multiple FIFO queues per input port

被引：6

作者：

Yeung, KL ^{[1
]}

Hai, S ^{[1
]}

机构：

[1] City Univ Hong Kong, Dept Elect Engn, Kowloon, Hong Kong

来源：

ELECTRONICS LETTERS | 1997年 / 33卷 / 19期

关键词：

asynchronous transfer mode; scheduling;

D O I：

10.1049/el:19971104

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Using two different packet scheduling policies, the maximum throughputs af an input-buffered ATM snitch with m-FIFO queues per input port are derived when the switch size is large.

引用

页码：1604 / 1606

页数：3

共 50 条

[1] Throughput analysis for input-buffered ATM switches with multiple FIFO queues per input port
Department of Electronic Engineering, City University of Hong Kong, Tat Chee Avenue, Kowloon Tong, Hong Kong
Electron Lett, 19 (1604-1606):
[2] Throughput analysis of input-buffered ATM switch
Makhamreh, II
IEE PROCEEDINGS-COMMUNICATIONS, 1998, 145 (01): : 15 - 18
[3] ATM input-buffered switches with the guaranteed-rate property
Hung, A
Kesidis, G
McKeown, N
THIRD IEEE SYMPOSIUM ON COMPUTERS AND COMMUNICATIONS, PROCEEDINGS, 1998, : 331 - 335
[4] Analysis of nonblocking ATM switches with multiple input queues
Nong, G
Muppala, JK
Hamdi, M
IEEE-ACM TRANSACTIONS ON NETWORKING, 1999, 7 (01) : 60 - 74
[5] Throughput analysis for multicast switches with multiple input queues
Song, M
Zhu, W
IEEE COMMUNICATIONS LETTERS, 2004, 8 (07) : 479 - 481
[6] Generalization of the Pollaczek-Khinchin formula for throughput analysis of input-buffered switches
Chang, CS
Lee, DS
Yu, CL
IEEE INFOCOM 2005: THE CONFERENCE ON COMPUTER COMMUNICATIONS, VOLS 1-4, PROCEEDINGS, 2005, : 960 - 970
[7] Matrix Unit Cell Scheduler (MUCS) for Input-Buffered ATM Switches
Duan, Haoran
Lockwood, John W.
Kang, Sung Mo
IEEE COMMUNICATIONS LETTERS, 1998, 2 (01) : 20 - 23
[8] Performance comparison of high-speed input-buffered ATM switches
Kim, HY
Ahmad, A
Oh, CW
Kim, K
IEEE ATM '97 WORKSHOP, PROCEEDINGS, 1997, : 505 - 513
[9] iiQueue, a QoS-oriented queue module for input-buffered ATM switches
Kang, SM
Duan, H
Lockwood, JW
Will, JD
ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE, 1997, : 2144 - 2147
[10] Discrete-time queueing models with feedback for input-buffered ATM switches
Laevens, K
Bruneel, H
PERFORMANCE EVALUATION, 1996, 27-8 : 71 - 87

← 1 2 3 4 5 →