Map-Reduce Inspired Loop Parallelization on CGRA

被引：0

作者：

Shao, Shengjia ^{[1
]}

Yin, Shouyi ^{[1
]}

Liu, Leibo ^{[1
]}

Wei, Shaojun ^{[1
]}

机构：

[1] Tsinghua Univ, Dept Microelect, Beijing 100084, Peoples R China

来源：

2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2014年

关键词：

Map-Reduce; CGRA; Loop Parallelization;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Our work(1) investigates how to map loops efficiently onto Coarse Grained Reconfigurable Architecture (CGRA). This paper examines the properties of CGRA and builds Map-Reduce inspired models for the loop parallelization problem. We solve our model using Geometric Programming methods to obtain best loop unrolling parameters. Those parameters are used in the Back-End process that followed. Experiment results show the proposed approach achieved up to 44% performance gain compared to a state-of-the-art loop unrolling scheme.

引用

页码：1231 / 1234

页数：4

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