共 50 条
- [31] Signed-Digit Addition Based on CNFETs and Ternary Logic FIFTY-SEVENTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, IEEECONF, 2023, : 1539 - 1546
- [32] Parallel quaternary signed-digit arithmetic operations: addition, subtraction, multiplication and division OPTICS AND LASER TECHNOLOGY, 1998, 30 (08): : 515 - 525
- [33] A novel past parallel signed-digit hybrid multiplication scheme for digital systems 2000 CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, CONFERENCE PROCEEDINGS, VOLS 1 AND 2: NAVIGATING TO A NEW ERA, 2000, : 630 - 635
- [35] High Performance Signed-Digit Decimal Adders 2009 IEEE INTERNATIONAL CONFERENCE ON ELECTRO/INFORMATION TECHNOLOGY, 2009, : 249 - 253
- [36] Efficient designs of one-step trinary signed-digit optical adders and multipliers based on new spatial encodings INTERNATIONAL JOURNAL OF OPTOELECTRONICS, 1998, 12 (03): : 79 - 90
- [37] Bidirectional conversion to minimum signed-digit representation 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 2413 - +
- [39] New Residue Signed-Digit Addition Algorithm PROCEEDINGS OF THE FUTURE TECHNOLOGIES CONFERENCE (FTC) 2019, VOL 2, 2020, 1070 : 390 - 396