A 30% Power Reduction Circuit Design for NAND Flash by Utilizing 1.2V I/O Power Supply to Bitline Path

This study proposes a low power circuit design for NAND Flash which is one of the power-hungry devices in datacenters. Power consumption in bit-line (BL) path can be reduced by 60% by utilizing 1.2V I/O power supply instead of 3V power supply, which contributes to reduction in the total power during read operation of 30%. The additional switching circuit only requires silicon area of 0.1mm(2) which is equivalent to 0.1% of a nominal die size of 100mm(2). To prevent degradation in sensing margin, the sensing node is pulled up to an internal supply voltage of 2V as used in the conventional design, which is regulated from 3V power supply, before starting sensing operation. This switching operation requires an additional timing of about 100ns which is equivalent to about 2% of an entire BL delay of 5 mu s. NAND flash interface does not have to be changed because the proposed design can work with the existing interface. BL path and the additional switches were designed in 65nm CMOS. A reduction in power in BL path of 60% was validated with SPICE simulation. As a result, the proposed design can contribute to power reduction in datacenter without any significant overhead on silicon area, BL delay and system design change.