The Assessment and Analysis About the Superiority of VHDL Language on FPGA Design and Development

被引：0
|
作者：
Luan, Xuqing [1 ]
机构：
[1] HFUT Sch Comp & Informat, Hefei 230009, Anhui, Peoples R China
来源：
PROCEEDINGS OF THE 2015 2ND INTERNATIONAL WORKSHOP ON MATERIALS ENGINEERING AND COMPUTER SCIENCES (IWMECS 2015) | 2015年 / 33卷
关键词：
VHDL; FPGA design; assessment; simulation;
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper is based on the effect that VHDL language on FPGA design and development, and we design the DDS module of FPGA by using the methods of designing. By research and analyse the The design of DDS module based on FPGA, we learn more about FPGA, visually and concretely. Also, We put forward the MidFilter based on VHDL language. The experiments show that the method can reduce deviation and improve the accuracy of the design.
引用
收藏
页码：157 / 162
页数：6
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