Impact Ionization and Hot-Carrier Degradation in Saddle-Fin and Buried-Gate Transistor of Dynamic Random Access Memory at Cryogenic Temperature

被引：5

作者：

Park, Jun ^{[1
]}

Lee, Namhyun ^{[2
]}

Kim, Gang-Jun ^{[2
]}

Choi, Hyun-Seok ^{[1
]}

Kim, Dae Hwan ^{[3
]}

Kim, Changhyun ^{[4
]}

Kang, Myounggon ^{[5
]}

Kim, Yoon ^{[1
]}

机构：

[1] Univ Seoul, Sch Elect & Comp Engn, Seoul 02504, South Korea

[2] Samsung Elect Co Ltd, Memory Div, Hwaseong 18448, South Korea

[3] Kookmin Univ, Sch Elect Engn, Seoul 02707, South Korea

[4] Pohang Univ Sci & Technol POSTECH, Dept Creat IT Engn, Pohang 37673, South Korea

[5] Korea Natl Univ Transportat, Dept Elect Engn, Chungju 380702, South Korea

来源：

IEEE ELECTRON DEVICE LETTERS | 2021年 / 42卷 / 05期

基金：

新加坡国家研究基金会;

关键词：

Impact ionization; Random access memory; Transistors; Scattering; Degradation; Threshold voltage; Logic gates; Hot-carrier degradation; DRAM reliability; buried-channel-array transistor; DRAM cell transistor; impact ionization; cryogenic computing system;

D O I：

10.1109/LED.2021.3067109

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Impact ionization and hot-carrier degradation (HCD) in buried-channel-array transistors (BCATs), which are used as the cell transistor, were investigated using sub-30 nm DRAM technology. The impact ionization rate was calculated by measuring the substrate current at different measurement conditions and modeled using an energy-driven model, which is suitable for short-channel transistors. In addition, HCD in BCAT under various operation conditions was analyzed. A multitrap-based approach, in which both interface- and oxide-trap generation were considered, was used to fit the experimental results. Our analysis and modeling results are useful in understanding and predicting the reliability of dynamic random access memory.

引用

页码：653 / 656

页数：4

共 7 条

[1] Data Retention Characteristics for Gate Oxide Schemes in Sub-50 nm Saddle-Fin Transistor Dynamic-Random-Access-Memory Technology
Ryu, Seong-Wan
Yoo, Minsoo
Choi, Deuksung
Cha, Seonyong
Jeong, Jae-Goan
JAPANESE JOURNAL OF APPLIED PHYSICS, 2011, 50 (04)
[2] Data retention characteristics for gate oxide schemes in sub-50nm saddle-fin transistor dynamic-random-access-memory technology
Semiconductor R and D Division, Hynix Semiconductor Inc., Icheon, Gyeonggi-do 467-701, Korea, Republic of
不详
Jpn. J. Appl. Phys., 4 PART 2
[3] Investigation of LDD n-MOSFET hot-carrier degradation with high gate-to-drain transverse field stressing at cryogenic temperature
Hsu, CT
Lau, MM
Yeow, YT
COMMAD 2000 PROCEEDINGS, 2000, : 157 - 160
[4] A low power L-shaped gate bipolar impact ionization MOSFET based capacitorless one transistor dynamic random access memory cell
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Singh, Jawar
JAPANESE JOURNAL OF APPLIED PHYSICS, 2021, 60 (06)
[5] Random Telegraph Signal-Like Fluctuation Created by Fowler-Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor
Kim, Heesang
Oh, Byoungchan
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Cha, Seon-Yong
Jeong, Jae-Goan
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JAPANESE JOURNAL OF APPLIED PHYSICS, 2010, 49 (09)
[6] Comparative study of p+/n+ gate modified saddle metal oxide semiconductor field effect transistors and p+/n+ gate bulk fin field effect transistors for sub-40 nm dynamic random access memory cell transistors
Park, Ki-Heung
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Japanese Journal of Applied Physics, 2008, 47 (7 PART 1): : 5365 - 5368
[7] Comparative study of p+/n+ gate modified saddle metal oxide semiconductor field effect transistors and p+/n+ gate bulk fin field effect transistors for sub-40 nm dynamic random access memory cell transistors
Park, Ki-Heung
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JAPANESE JOURNAL OF APPLIED PHYSICS, 2008, 47 (07) : 5365 - 5368

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