A Reconfigurable Co-processor for GMM-Based Classifier

被引：0
|
作者：
Wang, Wei [2 ]
Liang, Weiqian [1 ]
机构：
[1] Tsinghua Univ, Dept Elect Engn, Beijing 100084, Peoples R China
[2] Tsinghua Univ, Inst Microelect, Beijing 100084, Peoples R China
来源：
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2009年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents an efficient and reconfigurable co-processor to calculate Mahalanobis distance, which is the most computation-intensive part in the GMM (Gaussian Mixture Models)-based classifier. The Mahalanobis distance's calculation is divided into three parts (vector-vector subtraction, matrix-vector multiplication, and vector-vector multiplication) and these three parts can operate in a parallel way. The proposed architecture was implemented in Xilinx FPGA XC5VLX110T. Tested with a 358-state 3-mixture 39-feature 800-word HMM, co-processor operates at 35MHz to meet real-time requirement of speech recognition.
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收藏
页码：343 / +
页数：2
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