High-throughput bit processor for cryptography, error correction, and error detection

The product lifetime (time-in-market) of a high-end embedded SoC (System-on-Chip) can be rather short due to possible design changes, leading to a highly expensive SoC redesign. Most of the SoC redesign are induced by the requirements for function changes of non-programmable ASIC modules. Plenty of the non-programmable ASIC modules are used for bit-wise algorithms. It is thus necessary to offer programmable/flexible VLSI designs for the bit-wise algorithms. In this paper, we propose a programmable ASIP design for four types of the bit-wise algorithms: block ciphers, stream ciphers, Reed-Solomon (RS) Codes, and Cyclic Redundancy Check (CRC). We achieve this via finding out the algorithm similarities and the optimal parallel degree (128-bit) among the four types of bit-wise algorithms. The flexibility of our design can enlarge the range of applications and extend the time-in-market of a SoC. Besides, our design achieves ASIC-like performance such as 25.6 Gb/s for AES encryption, 17.6 Gb/s for RS(255,239) decoding, and 281.6 Gb/s for CRC calculation, etc with 0.19 mm(2) (28 nm) silicon area. Finally, we show that the performance of our design is sufficient for high-speed communication protocols like IEEE 802.11ad when running real-time AES, RS, and CRC simultaneously.