A 0.8 μm CMOS, 622 Mb/s SDH/SONET communication system

This paper describes a 0.8 mu m CMOS communication system designed for 622 Mb/s SDH/SONET Links. The single-chip system implements all line interface functions needed by the link The emitter performs parallel bus interface, parallel-to-serial conversion, and optional scrambling for sine testing. An output buffer to attack the laser driver is also included. The receiver performs post-amplification, clade recovery, frame detection and optional descrambling, followed by serial-to-parallel conversion and parallel bus interface.