Low power pipelined radix-2 FFT processor for speech recognition

被引：0

作者：

Wu, Gin-Der ^{[1
]}

Lei, Ying ^{[1
]}

机构：

[1] Natl Chi Nan Univ, Dept Elect Engn, Puli, Taiwan

来源：

PROCEEDINGS OF THE 2006 IEEE/SMC INTERNATIONAL CONFERENCE ON SYSTEM OF SYSTEMS ENGINEERING | 2006年

关键词：

FFT; radix-2; pipeline; Mel Frequency Cepstal Coefficient;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

It is important to develop a high-performance FFT/IFFT processor to meet the requirements of real-time, low area (low cast), and low power in different applications. In this paper, we proposed a radix-2 pipeline FFT processor for Mel Frequency Cepstal Coefficient (MFCC). Compared with [6]-[7], this novel architecture can reduce more power consumption. This approach is very attractive for MFCC speech feature extraction.

引用

页码：280 / +

页数：2

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