LSI design for MPEG-4 coding system

被引：0
|
作者：
Chang, YC [1 ]
Chao, WM [1 ]
Chen, LG [1 ]
机构：
[1] Natl Taiwan Univ, Dept Elect Engn, DSP IC Design Lab, Taipei 10764, Taiwan
来源：
2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS | 2004年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents an LSI design for MPEG-4 video coding. We adopt platform-based architecture with an embedded RISC core and efficient memory organization. A fast motion estimator architecture supporting predictive diamond search and spiral full search with halfway termination is implemented to make good compromise between compression performance and design cost. Several key modules are integrated into an efficient platform in hardware/software co-design fashion. With high degree of optimization in both algorithm and architecture levels, a cost-efficient video encoder LSI is implemented. It consumes 256.8mW at 40MHz and achieves real-time encoding of 30 CIF (352x288) frames per second.
引用
收藏
页码：453 / 456
页数：4
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