Strain and channel engineering for fully depleted SOI MOSFETs towards the 32 nm technology node

In this paper, we review different CMOS technologies used at CEA-LETI to improve hole and electron velocity for the 32 nm technology node Fully Depleted Silicon-On-Insulator (FDSOI) MOSFETs. The orientation, the strain and the material of the channel are the key parameters that have been tuned and optimized. Tensile strained SOI (sSOI) for nMOS and compressive Ge for pMOS are found to be promising channels for CMOS integration. They provide a 2 times (7.5 times) mobility improvement for electrons (holes), giving rise to well-balanced drain currents for n and pMOS. They also allow a tuning of the threshold voltage. The gate length and width scalabity of these technologies are also addressed. In particular, we detail the excellent performance of strained Si0.6Ge0.4 and sSOI down to 30 nm gate length. We also discuss the specifies of short channel transport in these channels: the role of the carrier mobility, the limiting scattering phenomena and the ballistic transport.