Technology-independent delay optimization of complex CMOS circuitries

被引：0

作者：

Seidel, PM ^{[1
]}

机构：

[1] So Methodist Univ, Dept Comp Sci & Engn, Dallas, TX 75275 USA

来源：

2002 45TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS | 2002年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

We extend the model of logical effort for technoogy-independent delay analysis and optimization of complex CMOS circuitries considering optimized gate sizing and buffer insertion. We are applying the proposed delay optimization procedure to the implementation of a fast dual path FP-adder with irregular structure.

引用

页码：314 / 317

页数：4

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