Feasibility of Embedded DRAM Cells on FinFET Technology

被引：12
|
作者：
Amat, Esteve [1 ]
Calomarde, Antonio [1 ]
Moll, Francesc [1 ]
Canal, Ramon [2 ]
Rubio, Antonio [1 ]
机构：
[1] Univ Politecn Cataluna, Dept Elect Engn, Barcelona, Spain
[2] Univ Politecn Cataluna, Comp Architecture Dept, Barcelona, Spain
来源：
IEEE TRANSACTIONS ON COMPUTERS | 2016年 / 65卷 / 04期
关键词：
FinFET; eDRAM and temperature; DEVICES; LOGIC;
D O I：
10.1109/TC.2014.2375204
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we analyze the suitability of implementing embedded DRAM (eDRAM) cells on FinFET technology compared to classical planar MOSFETs. The results show a significant improvement in overall cell performance for multi-gate devices. While pFinFET-based memories showed better cell behavior and variability robustness, mixed n/p FinFET cells had the highest working frequency and a negligible impact on degradation. Finally, we show that a multiple fin-height strategy can be used to reduce the layout area of the eDRAM cells (>10%).
引用
收藏
页码：1068 / 1074
页数：7
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