Evaluation of three 32-bit CMOS adders in DCVS logic for self-timed circuits (vol 33, pg 604, 1998)

被引：2

作者：

Ruiz, GA ^{[1
]}

机构：

[1] Univ Cantabria, Dept Elect & Comp, E-39005 Santander, Spain

来源：

关键词：

D O I：

10.1109/JSSC.2000.871333

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：1517 / 1517

页数：1

共 4 条

[1] Evaluation of three 32-bit CMOS adders in DCVS logic for self-timed circuits
Ruiz, GA
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (04) : 604 - 613
[2] Compact 32-bit CMOS adder in multiple-output DCVS logic for self-timed circuits
Ruiz, GA
Manzano, MA
IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2000, 147 (03): : 183 - 188
[3] Evaluation of dual-rail CMOS logic styles for self-timed circuits
Sartori, Giovani H.
Ribas, Renato P.
Reis, Andre I.
24TH NORCHIP CONFERENCE, PROCEEDINGS, 2006, : 197 - +
[4] Arithmetic logic circuits using self-timed bit level dataflow and early evaluation
Reese, RB
Thornton, MA
Traver, C
2001 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, ICCD 2001, PROCEEDINGS, 2001, : 18 - 23