Minimum energy consumption for rate monotonic scheduled tasks

被引:1
|
作者
Baskiyar, Sanjeev [1 ]
Huang, Chiao-Ching [1 ]
Tin-Yau Tam [2 ]
机构
[1] Auburn Univ, Dept Comp Sci & Software Engn, Auburn, AL 36849 USA
[2] Auburn Univ, Dept Math & Stat, Auburn, AL 36849 USA
基金
美国国家科学基金会;
关键词
CPU dynamic power consumption; Lagrange multiplier; Periodic tasks; DVFS;
D O I
10.1007/s00607-015-0475-4
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Limited battery power is a typical constraint in stand-alone embedded systems. One way to extend the battery lifetime is by reducing CPU power consumption. Because of the quadratic relationship between power consumption in CMOS circuits and CPU voltage, power reduction can be obtained by scaling down supply voltage, or dynamic voltage scaling. However, reducing supply voltage slows down CPU speed since supply voltage has a proportional relationship with CPU frequency. On the other hand, in any real-time embedded environment (especially hard real-time), timing constraints are critical. In this paper, we focus on dynamic energy reduction of tasks scheduled by rate monotonic (RM) algorithm in a hard real-time embedded environment. The RM algorithm preemptively schedules any set of periodic tasks by assigning higher priorities to frequent tasks. For any periodic task set that satisfies the CPU utilization bound, we determine the provably optimal scaling of the worst-case execution time of each task that consumes minimum dynamic energy while satisfying the utilization bound. As RM algorithm is widely used, we expect this work can lead to better energy reduction management and expectations.
引用
收藏
页码:661 / 684
页数:24
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