A Method for Automatically Implementing FPGA-based Pipelined Microprocessors

This paper presents a method of automatically generating the Verilog implementation of pipelined micro-processors. Based on the RTL descriptions of instructions, all types of hazards in pipelining are addressed optimally, especially in avoiding redundancy, reducing resource utilization and improving instruction throughput. Moreover, out-of-order execution mechanism is adopted in order to support multi-cycle instructions more efficiently. Besides, all the multiplexers and logics of control signals are analyzed and produced all by the method. The synthesized implementations of both pipelined controllers and datapaths are generated automatically, based on non-fixed architectures. A case study based on MIPS architecture not only explains the framework from input to simulation, but also illustrates the method gains almost equal performance with manual work.